1. Field of the Invention
The invention relates to the field of MOS dynamic memories.
2. Prior Art
Metal-oxide-semiconductor (MOS) dynamic memories are well-known and widely used. A substantial number of these memories employ memory cells which have a single MOS transistor and a capacitance means. These cells are disclosed in U.S. Pat. No. 3,387,286. Often these memory cells are connected to split bit-lines (bit-line halves), with each bit-line half being coupled to one input of a bistable sense amplifier having cross-coupled field-effect transistors. This configuration is shown in U.S. Pat. No. 3,514,765. An improvement to this configuration employing dummy cells to balance the input to the sense amplifier is disclosed in U.S. Pat. No. 3,678,473.
In recent years, these dynamic memories have steadily increased in capacity and density; 16K memories are now widely used. Currently there is an effort in the semiconductor industry to provide practical 64K (65,536 bits) memories. However, to do this it is necessary to optimize many of the circuits and circuit techniques employed in the prior art memories.
The present application discloses a 64K RAM having the general structure described in the above-referenced patents. A number of significant improvements are described which permit the practical realization of a 64K RAM. In the following description, a number of prior art patents are cited at appropriate places in the application. These patents and those cited above are the closest prior art known to the applicant.